1. Field of the Invention
The invention relates to an output transistor having resistance against electro static discharge (hereinafter, referred to simply as "ESD").
2. Description of the Related Art
There has been used metal-silicidation in CMOS and BiCMOS devices for reducing a diffusion layer resistance and a gate resistance to thereby ensure operation at a higher speed and higher integration. For instance, a layer resistance of a diffusion layer can be reduced down to one thirtieth by metal-silicidation, specifically from 200-300 .OMEGA./.quadrature. to 5-10 .OMEGA./.quadrature.. Hence, an operation speed or an integration density is improved by about 20% in comparison with devices to which metal-silicidation is not applied. If a particular layout is used, the improvement could reach about 60%, which means that metal-silicidation is quite useful for enhancing operation speed.
The latest MOS devices need to have a lightly doped drain (LDD) structure which is helpful for fabricating a device in smaller size. In LDD structure, source and drain region diffusion layers are designed to include diffusion layers having a lower impurity concentration in the vicinity of a gate electrode. Specifically, the diffusion layers have an impurity concentration one or two smaller in order than that of a usual diffusion layer. The LDD structure reduces influence by hot carriers which is accompanied with a channel length being shortened. Thus, the latest MOS transistors adopt both the metal-silicidation and LDD structure to thereby ensure a higher operation speed and higher integration.
Hereinbelow is explained ESD phenomenon with reference to FIGS. 1 and 2. FIG. 1 is a circuit diagram of a circuit doubling as an output transistor and an output protection circuit, and FIG. 2 is a cross-sectional view of a device corresponding to the circuit illustrated in FIG. 1. FIG. 2 illustrates CMOS transistor including a silicide and LDD structure. In the illustrated CMOS transistor, PMOS transistor is formed in a device region defined by p-type impurity region comprising p+ diffusion layers 6A and 7A and p- diffusion layers 6B and 7B, and an n-type well 3, and NMOS transistor is formed in a device region defined by n-type impurity region comprising n+ diffusion layers 8A and 9A and n- diffusion layers 8B and 9B, and a p-type silicon substrate 1. The layers 6B, 7B, 8B and 9B are all LDD layers. A silicide layer 13 entirely covers the p+ diffusion layers 6A, 7A and n+ diffusion layers 8A, 9A therewith. The source diffusion layer 7A of PMOS transistor is in electrical connection with a electric power source line Vdd through a source electrode 15C, and similarly, the source diffusion layer 8A of NMOS transistor is in electrical connection with a ground line GND through a source electrode 15A, and the drain diffusion layers 6A and 9A of PMOS and NMOS transistors are in electrical connection with an output terminal OUT through a drain electrode 15B. A gate of PMOS transistor is in electrical connection with the power source line Vdd, and a gate of NMOS transistor is in electrical connection with the ground line GND.
In ESD evaluation, four kinds of breakdown voltages at which a device is destroyed is tested by electrically connecting an ESD testing kit to the output terminal OUT, and applying static electricity which is positive (+) and negative (-) relative to a voltage at Vdd or GND, to the output terminal.
Hereinbelow, how a current flows when static electricity is applied to the output terminal OUT is explained with reference to FIG. 2. For instance, when static electricity positive relative to the ground line GND is applied to the output terminal OUT, an NPN type parasitic bipolar transistor defined by the drain diffusion layer 9A, the p-type substrate 1 and the source diffusion layer 8A of the NMOS transistor is turned on. That is, since a positive electricity is applied to the drain diffusion layer 9A acting as a collector, a reverse bias is applied to the transistor. At this time, since static electricity reaches hundreds of to thousands of volts, a breakdown takes place at a pn junction, and accordingly a current flows. The current raises a base voltage to thereby turn the NPN parasitic bipolar transistor on. Thus, the current flows from the source diffusion layer 8A to the ground line GND.
When static electricity negative relative to the ground line GND is applied to the output terminal OUT, a forward bias is applied to a diode defined by the drain diffusion layer 9A and the p-type substrate 1. Thus, the diode is turned on, and hence a current flows from the p-type substrate 1 to the output terminal OUT through the drain diffusion layer 9A.
A phenomenon which would take place when static electricity positive or negative relative to the power source line Vdd is applied to the output terminal OUT is the same as the above mentioned phenomenon except that the NPN parasitic bipolar transistor is replaced with PNP parasitic bipolar transistor. Hence, explanation is not made.
Herein, it should be noted that the parasitic bipolar transistor has a lateral structure. Hence, immediately after a voltage has been applied, a diffusion layer as a whole does not act as a collector, and thus is locally turned on. As a current is increased, on-state spreads over the entirety of a diffusion layer. Accordingly, the parasitic bipolar transistor needs to consider as an aggregate of a plurality of lateral transistors Tr1 to Trx having different base width, as illustrated in FIG. 2. The ESD immunity is dependent on how the on-state is dispersed in a diffusion layer when a voltage is applied thereto. The reason is as follows. If a current were concentrated into a certain lateral transistor, electric breakdown would take place in the lateral transistor. Accordingly, the ESD immunity could be obtained by propagating the on-state to all the other lateral transistors, if one of lateral transistors is turned on, to thereby avoid local concentration of current.
When MOS transistor having LDD and silicide as mentioned above is used as an output transistor, silicide might be a cause to lower the ESD immunity. For instance, suppose that there is not formed the silicide layer 13 in the NMOS transistor illustrated in FIG. 2, even if a positive static electricity is applied to the output terminal OUT, the concentration of current would not take place, because a diffusion layer has a high resistance. Hence, it is possible to have high ESD immunity. In contrast, when there is formed the silicide layer 13 as illustrated in FIG. 2, a voltage applied to the output terminal OUT could instantaneously reach the LDD layer 9B without a voltage drop. Since the LDD layer 9B has a low impurity concentration, the parasitic bipolar transistor Tr1 is first made to turn on among all the diffusion layers, and hence a current flows in the transistor Tr1. However, since a collector resistance is quite high and hence much heat is generated there, the parasitic bipolar transistor Tr1 is destroyed before the subsequent parasitic bipolar transistors Tr2 to Trx are made to turn on.
Hereinbelow is shown the results on ESD evaluation relating to presence or absence of silicide. Electric charge is charged into a capacitor having a capacity of 100 pF through a resistor of 1.5 k.OMEGA., and is connected to the output terminal OUT. In this arrangement, deterioration in performance of an output transistor has been observed before and after discharge of the capacity. It has been found that the ESD immunity of about -4000V could be maintained in diode operation regardless of presence or absence of silicide. In contrast, the circuit which could maintain the ESD immunity of about +4000V without silicide in parasitic bipolar transistor operation was destroyed at about +1000V by forming silicide therein. As is obvious from the above mentioned results, the ESD immunity of an output transistor is significantly concerned with the operation of a parasitic bipolar transistor.
In order to solve the above mentioned problem, a conventional semiconductor device has been designed to have MOS transistor including both silicide and LDD for an internal circuit thereof, taking integration and so on into consideration, and have another MOS transistor including no silicide for an output transistor, to thereby have the ESD immunity.
As mentioned earlier, when MOS transistor including LDD and silicide, as illustrated in FIG. 2, is used as an output transistor, there arises a problem that the ESD immunity is lowered, and hence the transistor is easily destroyed by static electricity.
In order to solve this problem, a conventional semiconductor device has been designed in such a manner that an output transistor thereof is not formed with silicide to have the ESD immunity. However, since an output transistor is a device for driving an external circuit, it is required to have a driving ability as well as the ESD immunity. As mentioned earlier, presence or absence of silicide makes a difference of about 20% in driving ability of MOS transistor. Thus, in order to satisfy a certain driving ability required, a transistor having no silicide has to be larger in size by 20% or more than a transistor having silicide. This is accompanied with an increase in cost in accordance with chip size.
Many methods have been suggested to fabricate a semiconductor device in which only output transistor has no silicide. However, such methods have excessive fabrication steps, which deteriorates a yield of fabrication. Specifically, a transistor used for an internal circuit is separately formed from an output transistor in the above mentioned methods. Hence, those methods have to have a step of forming source and drain diffusion layers of an output transistor with an internal circuit being covered with a mask, and some of those methods may need to further have a step of removing silicide formed on diffusion layers of an output transistor.
As a simple solution to the above mentioned problem, a transistor may be made larger in size with silicide being as it is, to thereby enhance resistance against destruction of a parasitic bipolar transistor in LDD layers. However, it has been confirmed in view of the experiments that a gate width has to be made two times longer or greater in order to have a certain ESD immunity. Thus, the above mentioned simple solution is accompanied with a problem of an increase in size of a transistor.
Japanese Unexamined Patent Publication No. 1-259560 has suggested a semiconductor integrated circuit device which includes an input and output protection circuit, an internal circuit, and a silicide layer formed on diffusion regions and polysilicon layers of the internal circuit. The silicide layer is not formed in diffusion regions of the input and output protection circuit.
Japanese Unexamined Patent Publication No. 4-234162 has suggested a semiconductor device including a semiconductor substrate having first electrical conductivity, a shallow junction region formed in the semiconductor substrate and having a certain depth and second electrical conductivity, a low-resistive wiring layer formed on the semiconductor substrate with an insulating layer sandwiched therebetween, said wiring layer being electrical connection with both the shallow junction region through contact holes formed throughout the insulating layer and an output terminal, and a deep junction region formed in the semiconductor substrate and having second electrical conductivity, said deep junction region having a region including a contact region in the shallow junction region, and also having a depth sufficient to surround junction destroyed portion generated, due to static electricity applied to the output terminal, in the semiconductor substrate through a contact portion of the low-resistive wiring layer and the shallow junction region.